A wide variety of applications exist in which it would be desirable for a machine to automatically recognize, analyze, and/or classify patterns existing in images which have been sensed and converted to some sort of matrix of electrical signals. Some of the simpler problems, which have been implemented with at least limited success by machines, include the recognition of alphanumeric characters and recognition or counting of certain particles, such as blood cells. (see e.g. U.S. Pat. Nos. 3,846,754 to Oka; 3,196,398 to Baskin; 3,473,789 to Sharp; 3,761,876 to Flaherty; 3,278,704 to Slotnick, and 3,899,771 to Saraga et al.)
Elaborate programs have been written for general purpose computers to perform pattern analysis and classification. The limited success of the general purpose computer to perform pattern analysis and classification is due to the extremely long processing times to process images with a large number of data points.
In recent years, a number of special purpose processors have been developed which implement mathematical techniques applicable to data in the form of images in order to transform the data points in the image to determine some of the characteristics of patterns displayed in the initial image array. One such digital image processing apparatus is disclosed in U.S. Pat. No. 4,363,104, issued to Nussmeier. Nussmeier discloses a video imaging system wherein the video image data, in the form of a matrix of points or picture elements (pixels) is multiplexed serially to each of a plurality of image processing modules. Each of the image processing modules contains its own bus control means for selecting the particular data words which lie in the assigned image region to be processed by that module, and memory means for storing the image data to be utilized by that particular module. While the Nussmeier system allows for parallel processing of portions of the entire image by each of the processing modules, a relatively complex hierarchical bussing system must be employed at the processor level. In addition, each of the processing modules must have its own bus controller, memory, internal data bus, and internal address bus in addition to the hardware which comprises the processing means.
U.S. Pat. No. 4,167,728, issued to Sternberg, and assigned to the assignee of the present invention, discloses a class of image analyzer processors employing a serial chain of substantially identical neighborhood transformation stages. The image data is serially shifted through a neighborhood extraction portion at each stage for sequentially accessing all the neighborhoods in the image matrix. Depending upon the states of the pixels contained in the neighborhood extraction portion, certain transformations are performed and the transformed output is passed on to the input of the succeeding stage. A central controller, which is coupled to all of the stages, defines all of the particular transformation analyses to be performed in each of the stages. The serial processor system disclosed in this patent and in related patent Nos. 4,174,514, 4,322,716, 4,395,699, and 4,414,685, obviate the need for the hardware and complex architecture required of the Nussmeier system, yet provide for cascaded transformation of a complete image by serially routing the image data stream from one stage to the next in the chain.
One object of the present invention is to provide an integrated high speed support system for the pipeline processing systems of the type disclosed in the Sternberg patents which allows for rapid routing of image data to and from the pipeline within the system.
Another object of the present invention is to provide an integrated image processing system of the type including the capability of combining or operating on a plurality of images simultaneously.
Another object of the present invention is to provide an image processing system capable of performing a programmed sequence of one or more different image processing operations on a serial stream of digital image data during a single pass through the system.
Another object of the present invention is to provide means for programming each of the pipeline processing stages in the pipeline for each processing cycle without materially affecting total processing time.
Another object of the present invention is to provide means for controlling the simultaneous flow of image data for multiple images through the processing system.